This invention relates in general to a computer of a data-driven (data flow) type, arid more particularly to a data-driven computer equipped with means which prevent packets from being inputted in excess of a system's throughput at the expense of the throughput of a system.
FIG. 13 is a block diagram showing the general construction of a typical conventional data-driven type computer which is disclosed in Japanese Patent Laid-open Application No. 220,328/1987. In this drawing figure, there are seen an input section designated by the reference numeral 2 which is adapted to receive packets inputted from the outside and bring them to the inside of a computer system, a program storage section designated by 3 adapted to store a data graph and add process information to the packets inputted, a firing process section designated by 4 adapted to a wait data to be inputted, an arithmetic operating section designated by 5 adapted to perform arithmetic operations on data, and an output section designated by 6.
The following introduces the operation of the data driven type computer.
The input section 2 functions to receive a packet consisting of a tag and data from an external device, and transmit it to the program storage section 3. This program storage section 3 serves to read program information in accordance with an address to which the packet is destined, and update the packet's tag to be sent to the firing process section 4. If the received tag is of binomial operation, the firing process section 4 serves to search another packet Forming a pair with the packet sent from among those stored in a firing process store section 4a, and if it is found, it is then sent together with the received packet to the arithmetic operation section 5. If it is not found, the received packet is then stored in the firing process store section 4a, and when it is decided to be necessary to produce a copy thereof from the packet's tag which was received, a packet of the same data yet having a different destination is generated therefrom and then sent together with the received packet to the arithmetic operating section 5. Then, the arithmetic operation section 5 operates in accordance with the tag of the received packet, which is to be transmitted to the output section 6. The packet received at the output section 6 is then sent either to the input section 2 or to the external device. Following is a repeated sequence of this processing.
According to such a construction of a typical conventional computer of a data-driven type as noted above, when packets are fed one after another to the input section 2 from an external unit up to the limit of throughput of the data-driven type computer system, and if still further packets are inputted from the input section 2, or if copies of packets are taken at the firing process section 4, the number of packets deposited in the inside of the data-driven computer system would exceed the system's throughput so that no further computing operation could in practice be made. Or else, in the data-driven type processor which employs a transfer control device known as an asynchronous delay line plus a C-device (see S. Komori et al. "An Elastic Pipeline Mechanism by Self-Timed Circuit", IEEE, JSSC, Vol. 23, No. 1; pp. 111-117 (Feb., 1988); Japanese Patent Applications Nos. 136,608/1985-136,610/1985), which is operates under similar conditions, it is inevitable that the speed of packet transfer may be substantially reduced.
The present invention is essentially directed to the provision of a useful solution of such problems noted above as encountered in a conventional data-driven type computer system which results in an improved data-driven type computer system having a sufficient throughput or a high arithmetic operating rate such that there is no real possibility apprehension that the quantity of packets will exceed the throughput of the system.